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The P89C669 represents the first Flash microcontroller based on Philips Semiconductors’ new 51MX core. The P89C669 features 96 kbytes of Flash program memory and 2 kbytes of data SRAM. In addition, this device is equipped with a Programmable Counter Array (PCA), a watchdog timer that can be configured to different time ranges through SFR bits, as well as two enhanced UARTs and byte based I2C-bus serial interface.
Key Features
- Extended features of the 51MX Core:
-- 23-bit program memory space and 23-bit data memory space
-- Linear program and data address range expanded to support up to 8 Mbytes each
-- Program counter expanded to 23 bits
-- Stack pointer extended to 16 bits enabling stack space beyond the 80C51 limitation
-- New 23-bit extended data pointer and two 24-bit universal pointers greatly improve C compiler code efficiency in using pointers to access variables in different spaces
- 100% binary compatibility with the classic 80C51 so that existing code is completely reusable
- Up to 24 MHz CPU clock with 6 clock cycles per machine cycle
- 96 kbytes of on-chip program Flash
- 2 kbytes of on-chip data RAM
- Programmable Counter Array (PCA)
- Two full-duplex enhanced UARTs
- Byte based Fast I2C serial interface (400 kbits/s) 2.2 Key benefits
Key Benefits
- Increases program/data address range to 8 Mbytes each
- Enhances performance and efficiency for C programs
- Fully 80C51-compatible microcontroller
- Provides seamless and compelling upgrade path from classic 80C51
- Preserves 80C51 code base, investment/knowledge, and peripherals and ASICs
- Supported by wide range of 80C51 development systems and programming tools vendors
- The P89C669 makes it possible to develop applications at lower cost and with a reduced time-to-market
Complete features
- Fully static
- Up to 24 MHz CPU clock with 6 clock cycles per machine cycle
- 96 kbytes of on-chip Flash with In-System Programming (ISP) and In-Application Programming (IAP) capability
- 2 kbytes of on-chip RAM
- 23-bit program memory space and 23-bit data memory space
- Four-level interrupt priority
- 32 I/O lines (4 ports)
- Three Timers: Timer0, Timer1 and Timer2
- Two full-duplex enhanced UARTs with baud rate generator
- Byte based Fast I2C-bus serial interface (400 kbits/s)
- Framing error detection
- Automatic address recognition
- Power control modes
- Clock can be stopped and resumed
- Idle mode
- Power-down mode
- Second DPTR register
- Asynchronous port reset
- Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with five Capture/Compare modules
- Low EMI (inhibit ALE)
- Watchdog timer with programmable prescaler for different time ranges (compatible with 8xC66x with added prescaler)
Emulation of this device is provided by
PDS51E
.
In addition, a daughterboard is required for emulation of this device. The daughterboards supporting the P89C669 device are:
PDE669
.
No programmer for this device is available from Acqura Systems
.
This device is also sometimes referred to by the following names : 89C669
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