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Datasheet |
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P89LPC901/902/903 microcontrollers datasheet |
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A summary of the datasheet is shown below. Get the full datasheet as a PDF. 
The P89LPC901/902/903 devices have byte-erasable Flash memory, enhanced timing functions and on-chip serial communications (LPC903). The are based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into this family in order to reduce component count, board space, and system cost.
Principal Features
-1 kB Flash code memory organised into 256-byte sectors, 16-byte pages and single byte erase functionality.
-128-byte RAM data memory.
-Two 16-bit counter/timers. Timer 0 pin (LPC901) may be configured to become a PWM output or counter input.
-23-bit system timer that can be used as a RTC (Real-Time Clock)
-One (LPC901) or two (LPC902/903) analog comparators with selectable inputs and reference source.
-Enhanced UART with fractional baud rate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities (LPC903).
-High-accuracy internal RC oscillator option, factory calibrated to 1 %, allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable. External crystal or clock option (LPC901).
-VDD operating range of 2.4 V to 3.6 V with 5 V tolerant I/O pins (may be pulled up or driven to 5.5 V).
-Up to six I/O pins when using internal oscillator and reset options.
-A variety of package options including SO8 and DIP8 (LPC901/902).
Additional Features
-A high performance 80C51 CPU provides instruction cycle times of 136 ns to 272 ns for all instructions except multiply and divide when using the internal 7.3728 MHz RC oscillator. A lower clock frequency for the same performance results in power savings and reduced EMI.
-In-Application Programming (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage.
-Serial Flash ICP allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs.
-Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from 8 values.
-Low voltage reset (Brownout detect) allows a graceful system shutdown when power fails. May optionally be configured as an interrupt.
-Idle and two different Power-down reduced power modes. Improved wake-up from Power-down mode (a low interrupt input starts execution). Typical Power-down current is less than 1 uA (total Power-down with voltage comparators disabled).
-Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.
-Configurable on-chip oscillator with frequency range options selected by user programmed Flash configuration bits. Oscillator options support frequencies from 20kHz to the maximum operating frequency of 12MHz (LPC901/906).
-Programmable port output configuration options:
- quasi-bidirectional
- open drain
- push-pull
- input-only
-Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.
-LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip.
-Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times.
-Only power and ground connections are required to operate the device when on-chip oscillator and reset options are selected.
-Four interrupt priority levels.
-Two (LPC901), three (LPC903), or five (LPC902) keypad interrupt inputs.
-Second data pointer.
-Schmitt trigger port inputs.
-Emulation support with Philips PDS900.
See the full datasheet as a PDF
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